Scalable Bus Structure

ABSTRACT

A method of communicating over a bus is disclosed and includes transmitting a first data type in a first type field over a first sub-channel of a transmit channel of the bus while concurrently transmitting a second data type in a second type field over a second sub-channel of the transmit channel of the bus. The method also includes receiving data over a receive channel of the bus while transmitting the first data type and the second data type over the transmit channel.

RELATED APPLICATION

This application claims priority from and is a continuation of priorapplication Ser. No. 11/565,041, filed Nov. 30, 2006, which claimspriority from and is a continuation of prior application Ser. No.10/921,053, filed Aug. 17, 2004, which claims priority from and thebenefit of U.S. Provisional Ser. No. 60/542,114, filed Feb. 4, 2004.

FIELD

The present disclosure relates generally to digital systems, and morespecifically, to a scalable bus structure.

BACKGROUND

Computers have revolutionized the electronics industry by enablingsophisticated processing tasks to be performed quickly. Thesesophisticated tasks may be performed by systems containing a high numberof complex components that communicate with one another in a fast andefficient manner using a bus. A bus is a channel or path betweencomponents in a computer, a computer subsystem, a computer system, orother electronic system.

Many buses resident in a computer have traditionally been implemented asshared buses. A shared bus provides a means for any number of componentsto communicate over a common path or channel. In recent years, sharedbus technology has been supplemented by point-to-point switchingconnections. Point-to-point switching connections provide a directconnection between two components on the bus while they arecommunicating with each other. Multiple direct links may be used toallow several components to communicate at the same time.

A common configuration for a computer includes a microprocessor withsystem memory. A high bandwidth system bus may be used to supportcommunications between the two. In addition, there may also be aperipheral bus which is used to transfer data to peripherals. In somecases, there may also be a configuration bus which is used for thepurpose of programming various resources. Bridges may be used toefficiently transfer data between the higher and lower bandwidth buses,as well as provide the necessary protocol translation. Each of thesebuses has been implemented with different protocols and may have a widevariation in performance requirements between them.

The use of multiple bus structures in a computer has provided a workablesolution for many years. However, as area and power emerge as the majordesign considerations for integrated circuits, it is becomingincreasingly desirable to reduce the complexity of the bus structure.

SUMMARY

In a particular embodiment, a method of communicating over a busincludes transmitting a first data type in a first type field over afirst sub-channel of a transmit channel of the bus while concurrentlytransmitting a second data type in a second type field over a secondsub-channel of the transmit channel of the bus. The method also includesreceiving data over a receive channel of the bus while transmitting thefirst data type and the second data type over the transmit channel.

In another particular embodiment, a method of communicating dataincludes during a first time period, communicating first data over afirst number of sub-channels of a transmit channel to a receivingcomponent. The method also includes during a second time period,communicating second data over a second number of sub-channels of thetransmit channel to the receiving component. The first number ofsub-channels and the second number of sub-channels are independentlyselectable from each other, where the second number of sub-channels isselectable from a total number of sub-channels available fortransmission, and where each sub-channel is operable to carry addressinformation, control signals, and write data.

In yet another particular embodiment, a method of communicating dataincludes determining a first number of sub-channels of a transmitchannel that are available for transmission of data from a sendingcomponent to a receiving component. The method also includes determininga second number of sub-channels of a receive channel that are availablefor transmission of data from the receiving component to the sendingcomponent. The method also includes sending data concurrently over eachof the first number of sub-channels, and receiving data concurrentlycommunicated over each of the second number of sub-channels.

In another particular embodiment, a method of communicating dataincludes receiving at a bridge multiple data types from a sendingcomponent over a plurality of sub-channels of a first bus, where eachsub-channel is operable to carry address information, control signals,and write data. The method also includes transmitting the multiple datatypes from the bridge to a receiving component over a second bus, wherethe first bus has a first bandwidth and the second bus has a secondbandwidth, where the first bandwidth is greater than the secondbandwidth.

In yet another particular embodiment, a processing system includes asending component configured, during a first time period, to communicatefirst data over a first number of sub-channels of a transmit channel toa receiving component and configured, during a second time period, tocommunicate second data over a second number of sub-channels of thetransmit channel to the receiving component. The first number ofsub-channels and the second number of sub-channels are independentlyselectable from each other, where the second number of sub-channels isselectable from a total number of sub-channels available fortransmission, and where each sub-channel is operable to carry addressinformation, control signals, and write data.

It is understood that other embodiments of the present invention willbecome readily apparent to those skilled in the art from the followingdetailed description, wherein various embodiments of the invention areshown and described by way of illustration. As will be realized, theinvention is capable of other and different embodiments and its severaldetails are capable of modification in various other respects, allwithout departing from the spirit and scope of the present invention.Accordingly, the drawings and detailed description are to be regarded asillustrative in nature and not as restrictive.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present invention are illustrated by way of example, andnot by way of limitation, in the accompanying drawings, wherein:

FIG. 1 is a conceptual block diagram illustrating an example of apoint-to-point connection over a two channel bus between two componentsin a processing system;

FIG. 2 is a timing diagram showing a read and write operation betweentwo components in a processing system having a point-to-point connectionover a two channel bus;

FIG. 3 is a conceptual block diagram illustrating an example of apoint-to-point connection over a high performance two channel busbetween two components in a processing system;

FIG. 4 is a conceptual block diagram illustrating the time divisionmultiplexed nature of the high performance bus of FIG. 3;

FIG. 5 is a conceptual block diagram illustrating an example of apoint-to-point connection over a low bandwidth two channel bus betweentwo components in a processing system;

FIG. 6 is a conceptual block diagram illustrating the time divisionmultiplexed nature of the low bandwidth bus of FIG. 5; and

FIG. 7 is a conceptual block diagram illustrating an example of apoint-to-point connection between a high performance component and alower bandwidth component through a bridge.

DETAILED DESCRIPTION

The detailed description set forth below in connection with the appendeddrawings is intended as a description of various embodiments of thepresent invention and is not intended to represent the only embodimentsin which the present invention may be practiced. The detaileddescription includes specific details for the purpose of providing athorough understanding of the present invention. However, it will beapparent to those skilled in the art that the present invention may bepracticed without these specific details. In some instances, well-knownstructures and components are shown in block diagram form in order toavoid obscuring the concepts of the present invention. Acronyms andother descriptive terminology may be used merely for convenience andclarity and are not intended to limit the scope of the invention.

Various components in a processing system may communicate over a bus.The bus may be scalable in terms of width and clock frequency to supportthe bandwidth requirements of the various components. The bus may alsouse a common architecture and signaling protocol for all scalableconfigurations. This may be achieved by reducing the signaling protocolof the bus to only those signals necessary to either transmit or receiveinformation.

The bus may be configured with a “transmit channel” that provides ageneric medium for broadcasting information from a sending component toa receiving component using the same signaling protocol in a timedivision multiplexed fashion. A “receive channel” may also use the samesignaling protocol to broadcast information from the receiving componentto the sending component.

FIG. 1 is a conceptual block diagram illustrating this fundamentalconcept. A point-to-point connection over a bus between two componentsis shown in a processing system. The processing system 100 may be acollection of components that cooperate to perform one or moreprocessing functions. Typically, the processing system will be acomputer, or resident in a computer, and capable of processing,retrieving and storing information. The processing system may be astand-alone system. Alternatively, the processing system may be embeddedin any device, including by way of example, a cellular telephone.

In one embodiment of the processing system 100, the bus 106 is adedicated bus between the sending component 102 and the receivingcomponent. In another embodiment of the processing system 100, thesending component 102 communicates with the receiving component 104 witha point-to-point connection over the bus 106 through a bus interconnect(not shown). Moreover, as those skilled in the art will readilyappreciate, the inventive aspects described throughout this disclosureare not limited to a dedicated bus or point-to-point switchingconnection, but may be applied to any type of bus technology including,by way of example, a shared bus.

The sending component 102 may be any type of bus mastering componentincluding, by way of example, a microprocessor, a digital signalprocessor (DSP), a direct memory access controller, a bridge, aprogrammable logic component, discrete gate or transistor logic, or anyother information processing component.

The receiving component 104 may be any storage component, including, byway of example, registers, memory, a bridge, or any other componentcapable of retrieving and storing information. The storage capacity ateach address location of the receiving component may vary depending onthe particular application and the overall design constraints. For thepurposes of explanation, the receiving component will be described witha storage capacity of 1-byte per address location.

The sending component 102 may read from or write to the receivingcomponent 104. In the case where the sending component 102 writes to thereceiving component 104, the sending component may broadcast an addresslocation, the appropriate control signals, and the payload to thereceiving component 104 on the transmit channel 108. The “payload”refers to the data associated with a particular read or write operation,and in this case, a write operation.

The control signals may include transfer qualifiers. The term “transferqualifier” refers to a parameter that describes an attribute of a readoperation, a write operation, or another bus related operation. In thiscase, the transfer qualifiers may include a “payload size signal” toindicate the number of data bytes contained in the payload. If thepayload is multiple bytes, then the receiving component 104 may storethe payload in a block of sequential address locations beginning withthe address location broadcast on the transmit channel 108. By way ofexample, if the sending device 102 broadcasts an address location 100_(HEX) followed by a 4-byte payload, the receiving component 104 maywrite the payload to a block of sequential address locations starting at100 _(HEX) and ending at 103 _(HEX).

The control signals may also include write byte enables. “Write byteenables” may be used to indicate which byte lanes on the transmitchannel 108 will be used to broadcast the payload for a write operation.By way of example, a 2-byte payload broadcast on an 32-bit transmitchannel 108 may use 2 of the 4 byte lanes. The write byte enables may beused to indicate to the receiving component 104 which of the 2 bytelanes on the transmit channel 108 will be used to broadcast the payload.

In the case where the sending component 102 reads from the receivingcomponent 104, the address location and the appropriate transferqualifiers may be the only information that needs to be broadcast on thetransmit channel 108. The transfer qualifiers may include a payload sizesignal to indicate the number of data bytes contained in the payload.The receiving component 104 may acknowledge the broadcast and send thepayload on the receiving channel 110. If the payload is multiple bytes,then the receiving component 104 may read the payload from a block ofsequential address locations beginning with the address locationbroadcast on the transmit channel 108. By way of example, if the sendingdevice 102 broadcasts an address location 200 _(HEX) and requests a4-byte payload, the receiving component 104 may retrieve the payloadfrom a block of sequential address locations starting at 200 _(HEX) andending at 203 _(HEX).

In the embodiment of the processing system described thus far, thesending component 102 has total control of the transmit channel 108 andmay broadcast one or more address locations with their associatedcontrol signals prior to, during, or after an active write operation.Also, the transmit and receive channels 108 and 110 are totallyindependent, and thus, the broadcasting of address locations, controlsignals, and write data by the sending component may coincide with thebroadcasting of read data by the receiving component 104. “Write data”refers to data broadcast by the sending component 102, and “read data”refers to data read from the receiving component 104 and broadcast onthe receiving channel 110.

An implicit addressing scheme may be used to control the sequence ofread and write data operations on the transmit and receive channels 108and 110. By way of example, if the sending component 102 initiatesmultiple write operations by broadcasting a series of address locationswith the appropriate control signals on the transmit channel 108, thesending component 102 will broadcast the payload for each writeoperation in the same sequence in which the address locations arebroadcast. Similarly, if the sending component 102 initiates multipleread operations by broadcasting a series of address locations with theappropriate control signals, the receiving component 104 will retrievethe payload for each read operation in the same sequence in which itreceives the address locations.

“Transfer tags” may be used as an alternative to this implicitaddressing scheme. The sending component 102 may assign a transfer tagfor each read and write operation. The transfer tag may be included inthe transfer qualifiers broadcast on the transmit channel 108. In thecase of a write operation, the sending component 102 may send thetransfer tag with the payload, and the receiving component 104 may usethe transfer tag recovered from the transfer qualifiers to identify thepayload. In the case of a read operation, the receiving component 104may send the recovered transfer tag with the payload, and the sendingcomponent may use the transfer tag to identify the payload.

The various concepts described thus far may be implemented using anynumber of protocols. In the detailed description to follow, an exampleof a bus protocol will be presented. This bus protocol is beingpresented to illustrate the inventive aspects of a processing system,with the understanding that such inventive aspects may be used with anysuitable protocol. The basic signaling protocol for the transmit channelis shown below in Table 1. Those skilled in the art will readily be ableto vary and/or add signals to this protocol in the actual implementationof the bus structure described herein.

TABLE 1 Signal Definition Driven By Clock the reference clock signalsystem Valid valid information is being sending component broadcast onthe transmit channel Type (2:0) indicates the type of sending componentinformation being broadcast Transfer Ack indicates receiving componentreceiving component is ready to receive write data Transmit Channelchannel driven by the sending sending component component to broadcastinformation

The same signaling protocol may be used for the receive channel as shownbelow in Table 2.

TABLE 2 Signal Definition Driven By Clock the reference clock signalsystem Valid valid information is being Receiving component broadcast onthe receive channel Type (2:0) Indicates the type of Receiving componentinformation being broadcast Transfer Ack indicates sending componentsending component is ready to receive read data Receive Channel channeldriven by the Receiving component receiving component to broadcastinformation

The definition of the Type field used in this signaling protocol isshown in Table 3.

TABLE 3 Type Value Definition 000 Reserved 001 Valid Write AddressLocation 010 Valid Write Control Signals 011 Valid Write Data 100Reserved 101 Valid Read Address Location 110 Valid Read Control Signals111 Valid Read Data

The definition of the Valid and Transfer Ack signals in this signalingprotocol is shown in Table 4.

TABLE 4 Valid; Transfer Ack Definition 0; 0 Valid information is notbeing broadcast, and the component at the other end is not ready toreceive a broadcast 0; 1 Valid information is not being broadcast, butthe component at the other end is ready to receive a broadcast 1; 0Valid information is being broadcast, but the component at the other endis not ready to receive a broadcast 1; 1 Valid information is beingbroadcast, and the component at the other end is ready to receive abroadcast

FIG. 2 is a timing diagram illustrating a read and write operation overa 32-bit transmit channel and a 32-bit receive channel. A System Clock202 may be used to synchronize communications between the sendingcomponent and the receiving component. The System Clock 202 is shownwith eleven clock cycles, with each cycle numbered sequentially for easeof explanation.

A write operation may be initiated by the sending component during thesecond clock cycle 203. This may be achieved by asserting the Validsignal 204 and setting the Type field 206 to signal a broadcast of anaddress location for a write operation. The address location may also bebroadcast over the Transmit Channel 208 to the receiving component. Inresponse to this broadcast, the receiving component stores the addresslocation in its address queue.

The broadcast of the address location may be followed by a controlsignal broadcast for the write operation in the third clock cycle 205.The sending component may alert the receiving component of the controlsignal broadcast by keeping the Valid signal 204 asserted and changingthe Type field 206 appropriately. The control signal broadcast mayinclude the transfer qualifiers and the write byte enables for the writeoperation. In this case, the transfer qualifiers may include a payloadsize signal indicating an 8-byte payload. The write byte enables mayindicate that the 8-byte payload will be transmitted on all byte lanesof the Transmit Channel 208. The receiving component may determine fromthis information that the payload broadcast will be broadcast over twoclock cycles.

The first 4-bytes of the payload for the write operation may bebroadcast on the Transmit Channel 208 during the fourth clock cycle 207.The sending component may alert the receiving component of the payloadbroadcast by keeping the Valid signal 204 asserted and changing the Typefield 206 to signal a payload broadcast. In the absence of transfertags, the receiving component recognizes the write data as the first4-bytes of the payload based on the implicit addressing scheme discussedearlier. In response to this broadcast, the first 4-bytes of the payloadmay be written to the receiving component.

In the following clock cycle 209, the Valid signal 204 and the Typefield 206 remains unchanged as the second 4-bytes of the payload isbroadcast on the Transmit Channel 208. However, the receiving componenthas disserted the Transfer Ack signal 210 indicating that it cannotaccept the broadcast. The sending component may detect that the TransferAck signal 210 is not asserted at the end of this fifth clock cycle 209,and repeat the broadcast of the second 4-bytes of the payload in thefollowing clock cycle 211. The sending component may continue tobroadcast the second 4-bytes of the payload every clock cycle until thesending component detects the assertion of the Transfer Ack signal 210from the receiving component. In this case, only one repeat broadcast isrequired. The second 4-bytes of the payload may be written to thereceiving component in the sixth clock cycle. At the end of the sixthclock cycle 211, the sending component detects the assertion of theTransfer Ack signal 210, and determines that the broadcast has beenreceived.

A read operation may be initiated by the sending component during theseventh clock cycle 213. This may be achieved by asserting the Validsignal 204 and setting the Type field 206 to signal the broadcast of anaddress location for a read operation. The address location may then bebroadcast over the Transmit Channel 208 to the receiving component. Inresponse to this broadcast, the receiving component stores the addresslocation in its address queue.

The broadcast of the address location may be followed by a controlsignal broadcast for the read operation in the eighth clock cycle 215.The sending component may alert the receiving component of the controlsignal broadcast by keeping the Valid signal 204 asserted and changingthe Type field 206 appropriately. The control signal broadcast mayinclude the transfer qualifiers for the read operation. In this case,the transfer qualifiers may include a payload size signal indicating a4-byte payload. The receiving component may determine from thisinformation that the payload broadcast can be broadcast over one clockcycle.

Due to the read latency of the receiving component, a several clockcycle delay may be experienced before the read data is available. Oncethe 4-byte payload is available, the receiving component may assert theValid signal 212 and assert the Type field 214 signaling a payloadbroadcast on the Receive Channel 216. Since the Transfer Ack signal 218is asserted by the sending component, the broadcast of the payload maybe completed in one clock cycle. The receiving component detects theassertion of the Transfer Ack signal 218 at the end of the tenth clockcycle 219, and thereby determines that the broadcast of the payload wassuccessful.

FIG. 3 is conceptual block diagram illustrating a point-to-pointconnection between two components over a high performance bus. Thetransmit and receive channels 108 and 110 of the high performance busmay be implemented as multiple sub-channels with each sub-channel being32-bits wide. In actual implementations, the number of sub-channels andthe width of each sub-channel may vary depending on the performancerequirements of the particular application. In this example, thetransmit channel includes 4 32-bit sub-channels 108 a-108 d, and thereceive channel includes 2 32-bit sub-channels 110 a-110 b. Thisimplementation may be suitable, by way of example, for a system bus in acomputer, or any other high performance bus. The term “sub-channel”refers to a group of wires or conductors which may be controlledindependently of the other wires or conductors in the channel. Thismeans that each sub-channel may be provided with independent signalingcapability.

This high performance bus may be used by the sending component 102 tosimultaneously broadcast several combinations of information. By way ofexample, the sending component may broadcast a 32-bit address location,32-bits of control signals including transfer qualifiers and write byteenables, and 8-bytes of write data within a single clock cycle. In thecase of the receive channel 110, 8-bytes of read data may be broadcastfrom the receiving component 104 to the sending component 102 within asingle clock cycle.

Since the various embodiments of the processing system described thusfar do not include any other type of information broadcast on thereceive channel 110 other than read data, there is no need forsub-channels. A single 64-bit receive channel may be implemented toreduce the signaling requirements (i.e., no sub-channels). However, insome embodiments of the processing system, the Type field in thesignaling protocol may be extended to allow for the broadcast of otherinformation. By way of example, a “write response” may be broadcast onthe receive channel 110 to signal the sending component that the datahas been written to the receiving component 104. The write responsecould be broadcast on the receive channel 110 using one of the reservedType fields. In that case, it may be useful to have two independentlycontrolled 32-bit sub-channels so that read data and a write responsemay be broadcast on the receive channel 110 simultaneously. With 232-bit sub-channels, it may then be possible to simultaneously broadcast4-bytes of read data, 2-bytes of read data and a 32-bit write response,or 2 32-bit write responses. A single 64-bit receive channel 110, on theother hand, may be only able to support read data or write responses inany given clock cycle.

In a similar manner, the transmit channel may also be extended toinclude the broadcast of other types of information that are common inmany bus protocols, such as standard commands. By way of example, amicroprocessor attached to a bus may need to broadcast information toother components in the system such as a TAB Sync command, or a TABinvalidate command. These commands may be classified in the Type fieldwithout the need for additional signaling.

FIG. 4 is a block diagram illustrating the time division multiplexednature of a transmit channel 108 with 4 sub-channels 108 a-108 d. Inthis example, a complete 8-byte payload broadcast may be completedacross the 4 sub-channels within a single clock cycle. Morespecifically, during the first clock cycle 401, the sending componentmay broadcast a 32-bit address location on the first sub-channel 108 aand 32-bits of control signals on the second sub-channel 108 b for thefirst write operation. The sending component may also broadcast, duringthe same clock cycle, the higher order 4-bytes of the payload on thethird sub-channel 108 c and the lower order 4-bytes of the payload onthe fourth sub-channel 108 d. Each sub-channel 108 a-108 d may beprovided with independent signaling capability, and in the casedescribed above, assert the Valid signal with the appropriate Type fieldfor each sub-channel.

With the Transfer Ack asserted for each sub-channel 108 a-108 d at theend of the first clock cycle 401, two read operations may be initiatedby the sending component during the second clock cycle 403. This may beachieved by broadcasting a 32-bit address location on the firstsub-channel 108 a and 32-bits of control signals on the secondsub-channel 108 b for the first read operation, with the appropriatesignaling on each sub-channel 108 a-108 b. The sending component mayalso broadcast a 32-bit address location on the third sub-channel 108 cand 32-bits of control signals on the fourth sub-channel 108 d for thesecond read operation, again with the appropriate signaling for thesub-channels 108 c-108 d

With the Transfer Ack asserted for each sub-channel 108 a-108 d at theend of the second clock cycle, a second write operation and third readoperation may be initiated by the sending component during the thirdclock cycle 405. This may be achieved by broadcasting a 32-bit addresslocation on the first sub-channel 108 a and 32-bits of control signalson the second sub-channel 108 b for the second write operation, with theappropriate signaling on each sub-channel 108 a-108 b. The sendingcomponent may also broadcast a 32-bit address location on the thirdsub-channel 108 c and 32-bits of control signals on the fourthsub-channel 108 d for the third read operation, again with theappropriate signaling for the sub-channels 108 c-108 d.

In this example, at the end of the third clock cycle 405, the TransferAck signal is asserted on the first and second sub-channels 108 a and108 b, but not on the third and fourth sub-channels 108 c and 108 d. Thesending component may detect that the Transfer Ack on the third andfourth sub-channels 108 c and 108 d are not asserted, and thus,determine that the address location and the control signals for thethird read operation should be rebroadcast. The address location and thecontrol signals for the third read operation are shown being broadcastduring the fourth clock 407 on the third and fourth sub-channels 108 cand 108 d, respectively, but may be rebroadcast on any sub-channelsduring any subsequent clock cycle.

In the above example, the receiving component is configured to eitheraccept or reject both the address location and the control signals forthe third read operation. However, in some embodiments of the processingsystem, the receiving component may be configured to accept the addresslocation and reject the control signals, or vice versa, for the sameread or write operation. Similarly, the receiving component may beconfigured to accept or reject the higher or lower order bytes of thepayload individually. In this case, there needs to be a way to tie arebroadcast of say the control signals for the third read operation tothe address location for the same operation previously broadcast. Thismay be achieved in a variety of ways. By way of example, once an addresslocation for a read or write operation is sent and acknowledged by thereceiving component, the address for the next read or write operation isnot broadcast until the control signals associated with the current reador write operation request is received and acknowledged by the receivingcomponent.

During the fourth clock cycle 407, the sending component may broadcastthe payload for the second write operation and attempt for the secondtime to initiate a third read operation. This may be achieved bybroadcasting the higher order 4-bytes of the payload on the firstsub-channel 108 a and the lower order 4-bytes of the payload on thesecond sub-channel 108 b for the second write operation, with theappropriate signaling on each sub-channel 108 a-108 b. The sendingcomponent may also rebroadcast the 32-bit address location on the thirdsub-channel 108 c and 32-bits of control signals on the fourthsub-channel 108 d for the third read operation.

In this high performance bus embodiment, the ordering of the read/writerequests may be implicit by position. The sending component maybroadcast the first read/write request on the first sub-channel 108 a,the second read/write request on the second sub-channel 108 b, the thirdread/write request on the third sub-channel 108 c, and the fourthread/write request on the fourth sub-channel 108 d. The receivingcomponent may process the requests based on this implicit positioning inorder to maintain sequential consistency. By way of example, if theaddress locations for the read and write operations initiated during thethird clock cycle 405 are the same, the receiving component may waituntil the data broadcast on the first and second sub-channels 108 a and108 b during the fourth clock cycle 407 is written to the addresslocation before providing the newly written data at this addresslocation to the receive channel for transmission to the sendingcomponent.

In the embodiment of the high performance bus described thus far, thewrite data does not need to be broadcast immediately following thebroadcast of the write operation request (i.e., the address location andcontrol signals). Other higher priority read operation requests and/orcommands may be interleaved with the write data broadcast on thetransmit channel 108. However, if the sending component interleaves theread operation requests and/or commands with the write data, then thesending component should be configured with an address back-offmechanism.

As described earlier in connection with FIG. 2, the sending componentsamples the Transfer Ack signal 210 following a broadcast on theTransmit Channel 208. If the sending component fails to detect anasserted Transfer Ack signal 210, then it may repeat the broadcastduring the following clock cycle. The broadcast may be repeated everyclock cycle until the sending component detects an asserted Transfer Acksignal 210. A problem may arise when the address queue is full during aread operation request, and therefore, cannot accept any more addresslocations. At the same time, the receiving component needs to completethe pending write operation in order to free up space in the addressqueue. In this case, the receiving component is said to be deadlocked.

The address back-off mechanism is designed to allow the write operationto be completed when the receiving component is in deadlock. This may beachieved by limiting the number of repeat broadcasts by the sendingcomponent in connection with a read operation request. If the receivingcomponent does not acknowledge a read operation request with a TransferAck signal within a certain number of clock cycles, then the sendingcomponent may abort the request by sending the remaining write data inplace of the address location for the current read operation request. Ifthere is not a pending write operation that needs to be completed, thenthe broadcast of the read operation request does not need to be aborted.The broadcast may continue until the receiving component acknowledgesthe request.

The address back-off mechanism may not be needed if the sendingcomponent does not interleave read operation requests with write data.That is, if the address location for a write operation is followedimmediately by the control signals, and then immediately followed by thewrite data, then the receiving component will never encounter deadlock.However, this may degrade the performance of the receive channel becausethe sending component may not be able to keep the pipeline of readoperations sufficient to fully utilize the bandwidth of the receivechannel.

FIG. 5 is a conceptual block diagram illustrating a point-to-pointconnection between two components over a low bandwidth bus. The lowbandwidth bus may be implemented with a single transmit channel 108 anda single receive channel 110 requiring fewer signals and resulting inlower power dissipation. In the example shown in FIG. 5, the sendingcomponent 102 may broadcast information to the receiving component 104over a 32-bit transmit channel 108, and the receiving component 104 maybroadcast information back to the sending component 102 over a 32-bitreceive channel 110. Alternatively, this same bus architecture may beimplemented with narrower bus widths.

Although this configuration continues to allow for the transmit andreceive channels 108 and 110 to broadcast information simultaneously,each read or write operation may now require multiple clock cycles asshown in the block diagram of FIG. 6. In this example, two clock cyclesare used to initiate a read operation. More specifically, a 32-bitaddress location may be broadcast on the transmit channel 108 in thefirst clock cycle 601, followed by 32-bits of control signals in thefollowing clock cycle 603. A 4-byte payload may be read from thereceiving component in response to this request and broadcast on thereceive channel 110 in the third clock cycle 605.

Concurrently with the broadcast of the payload on the receive channel,the sending component may initiate a write operation. In this case, thewrite operation uses three clock cycles. In the third clock cycle 605,the sending component broadcasts a 32-bit address location on thetransmit channel 108, followed by 32-bits of control signals in thefourth clock cycle 607, followed by a 4-byte payload in the fifth clockcycle 609.

In many processing systems, some devices may require a high bandwidthinterconnect while others can sufficiently operate with a much lowerbandwidth interconnect. By using a scalable bus architecture, theimplementation of bridges may be implemented with a common signalingprotocol. FIG. 7 is a conceptual block diagram illustrating apoint-to-point connection between two components through a bridge. Thebridge 702 may be used to interface a sending component 102 attached toa high performance bus to a receiving component 104 attached to a lowerbandwidth bus. The high performance bus may be implemented with atransmit channel 108 having 4 32-bit sub-channels 108 a-108 d and areceive channel 110 having 2 32-bit receive channels 110 a and 110 b.The lower bandwidth bus may be implemented with a single 32-bit transmitchannel 108′ and a single 32-bit receive channel 110′.

In this example, a write operation may be completed between the sendingdevice 102 and the bridge 702 within a single clock cycle using the 4transmit sub-channels 108 a-108 d of the high performance bus tobroadcast the address location, the control signals, and an 8-bytepayload as described earlier in connection with FIGS. 3 and 4. Thebridge 702 may buffer and broadcast the information to the receivingcomponent 104 over the 32-bit transmit channel 108′ of the lowerbandwidth bus in 4 clock cycles as described earlier in connection withFIGS. 5 and 6.

In the case of a read operation, an address location and the controlsignals may be broadcast by the sending component 102 to the bridge 702on 2 transmit sub-channels of the high performance bus within a singleclock cycle. The bridge 702 may buffer and broadcast this information tothe receiving component 104 over the 32-bit transmit channel 108′ in twoclock cycles. An 8-byte payload may then be broadcast from the receivingcomponent 104 to the bridge 702 on the 32-bit receive channel 110′,buffered in the bridge 702, and then broadcast by the bridge 702 to thesending component 102 on the two receive sub-channels 110 a and 110 b ina single clock cycle.

The various illustrative logical blocks, modules, and circuits describedin connection with the embodiments disclosed herein may be implementedor performed with a general purpose processor, a digital signalprocessor (DSP), an application specific integrated circuit (ASIC), afield programmable gate array (FPGA) or other programmable logiccomponent, discrete gate or transistor logic, discrete hardwarecomponents, or any combination thereof designed to perform the functionsdescribed herein. A general-purpose processor may be a microprocessor,but in the alternative, the processor may be any conventional processor,controller, microcontroller, or state machine. A processor may also beimplemented as a combination of computing components, e.g., acombination of a DSP and a microprocessor, a plurality ofmicroprocessors, one or more microprocessors in conjunction with a DSPcore, or any other such configuration.

The methods or algorithms described in connection with the embodimentsdisclosed herein may be embodied directly in hardware, in a softwaremodule executed by a processor, or in a combination of the two. Asoftware module may reside in RAM memory, flash memory, ROM memory,EPROM memory, EEPROM memory, registers, hard disk, a removable disk, aCD-ROM, or any other form of storage medium known in the art. A storagemedium may be coupled to the processor such that the processor can readinformation from, and write information to, the storage medium. In thealternative, the storage medium may be integral to the processor. Theprocessor and the storage medium may reside in an ASIC. The ASIC mayreside in the sending and/or receiving component, or elsewhere. In thealternative, the processor and the storage medium may reside as discretecomponents in the sending and/or receiving component, or elsewhere.

The previous description of the disclosed embodiments is provided toenable any person skilled in the art to make or use the presentinvention. Various modifications to these embodiments will be readilyapparent to those skilled in the art, and the generic principles definedherein may be applied to other embodiments without departing from thespirit or scope of the invention. Thus, the present invention is notintended to be limited to the embodiments shown herein but is to beaccorded the widest scope consistent with the principles and novelfeatures disclosed herein.

1. A method of communicating over a bus, the method comprising:transmitting a first data type in a first type field over a firstsub-channel of a transmit channel of the bus while concurrentlytransmitting a second data type in a second type field over a secondsub-channel of the transmit channel of the bus; and receiving data overa receive channel of the bus while transmitting the first data type andthe second data type over the transmit channel.
 2. The method of claim1, wherein transmitting the first data type and the second data typefurther comprises transmitting address information, control information,or data information, wherein the address information comprises read orwrite address information, the control information comprises read orwrite control signals, and the data information comprises write data. 3.The method of claim 1, further comprising receiving a signal indicativeof out of order data.
 4. The method of claim 3, wherein the signalindicative of out of order data includes a transfer tag communicatedover the receive channel of the bus.
 5. The method of claim 1, furthercomprising receiving first return data over a first sub-channel of areceive channel of the bus and receiving second return data over asecond sub-channel of the receive channel.
 6. The method of claim 1,further comprising concurrently receiving data over the receive channelof the bus and transmitting multiple data types over at least one of thefirst sub-channel of the transmit channel of the bus and the secondsub-channel of the transmit channel of the bus.
 7. The method of claim1, further comprising receiving a payload over the receive channel andreceiving a transfer tag that identifies the payload over the receivechannel.
 8. The method of claim 1, further comprising sending a thirddata type over a third sub-channel of the transmit channel.
 9. A methodof communicating data, the method comprising: during a first timeperiod, communicating first data over a first number of sub-channels ofa transmit channel to a receiving component; and during a second timeperiod, communicating second data over a second number of sub-channelsof the transmit channel to the receiving component; wherein the firstnumber of sub-channels and the second number of sub-channels areindependently selectable from each other, wherein the second number ofsub-channels is selectable from a total number of sub-channels availablefor transmission, and wherein each sub-channel is operable to carryaddress information, control signals, and write data.
 10. The method ofclaim 9, wherein the first number of sub-channels is different than thesecond number of sub-channels.
 11. The method of claim 9, wherein thesecond number of sub-channels is selectable based on performancerequirements of an application.
 12. The method of claim 9, wherein afirst width of each of the first number of sub-channels is differentthan a second width of each of the second number of sub-channels.
 13. Amethod of communicating data, the method comprising: determining a firstnumber of sub-channels of a transmit channel that are available fortransmission of data from a sending component to a receiving component;determining a second number of sub-channels of a receive channel thatare available for transmission of data from the receiving component tothe sending component; sending data concurrently over each of the firstnumber of sub-channels; and receiving data concurrently communicatedover each of the second number of sub-channels.
 14. The method of claim13, further comprising dynamically changing the first number ofsub-channels or the second number of sub-channels in response to atraffic condition of the transmit channel.
 15. A method of communicatingdata, the method comprising: receiving at a bridge multiple data typesfrom a sending component over a plurality of sub-channels of a firstbus, wherein each sub-channel is operable to carry address information,control signals, and write data; and transmitting the multiple datatypes from the bridge to a receiving component over a second bus,wherein the first bus has a first bandwidth and the second bus has asecond bandwidth, wherein the first bandwidth is greater than the secondbandwidth.
 16. The method of claim 15, wherein each of the first bus andthe second bus is implemented with a common protocol.
 17. The method ofclaim 15, further comprising: receiving read data from the receivingcomponent at the bridge over the second bus; and sending the read datafrom the bridge to the sending component over the first bus.
 18. Themethod of claim 17, wherein the second bus includes a plurality ofsub-channels.
 19. A processing system comprising: a sending componentconfigured, during a first time period, to communicate first data over afirst number of sub-channels of a transmit channel to a receivingcomponent and configured, during a second time period, to communicatesecond data over a second number of sub-channels of the transmit channelto the receiving component; wherein the first number of sub-channels andthe second number of sub-channels are independently selectable from eachother, wherein the second number of sub-channels is selectable from atotal number of sub-channels available for transmission, and whereineach sub-channel is operable to carry address information, controlsignals, and write data.
 20. The processing system of claim 19, whereinthe first number of sub-channels is different than the second number ofsub-channels.
 21. The processing system of claim 19, wherein the secondnumber of sub-channels is selectable based on performance requirementsof an application.
 22. The processing system of claim 19, wherein afirst width of each of the first number of sub-channels is differentthan a second width of each of the second number of sub-channels.
 23. Anapparatus comprising: means for transmitting multiple data types from asending component to a bridge over a plurality of sub-channels of afirst bus, wherein each sub-channel is operable to carry addressinformation, control signals, and write data; means for transmitting themultiple data types from the bridge to a receiving component over asecond bus, wherein the first bus has a first bandwidth and the secondbus has a second bandwidth, wherein the first bandwidth is greater thanthe second bandwidth; means for sending read data from the receivingcomponent to the bridge over the second bus; and means for sending theread data from the bridge to the sending component over the first bus.24. The apparatus of claim 23, wherein each of the first bus and thesecond bus is implemented with a common protocol.
 25. The apparatus ofclaim 23, wherein the second bus comprises a plurality of sub-channels.